View AD5172BRMZ100-RL7_3768604.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

256-position, one-time programmable, dual-channel, i 2 c digital potentiometers ad5172/ad5173 rev. h information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2009 analog devices, inc. all rights reserved. features 2-channel, 256-position potentiometers one-time programmable (otp) set-and-forget resistance setting provides a low cost alternative to eemem unlimited adjustments prior to otp activation otp overwrite allows dynamic adjustments with user- defined preset end-to-end resistance: 2.5 k, 10 k, 50 k, and 100 k compact 10-lead msop: 3 mm 4.9 mm fast settling time: t s = 5 s typical on power-up full read/write of wiper register power-on preset to midscale extra package address decode pins: ad0 and ad1 (ad5173) single supply: 2.7 v to 5.5 v low temperature coefficient: 35 ppm/c low power: i dd = 6 a maximum wide operating temperature: ?40c to +125c applications systems calibration electronics level setting mechanical trimmers replacement in new designs permanent factory pcb setting transducer adjustment of pressure, temperature, position, chemical, and optical sensors rf amplifier biasing automotive electronics adjustment gain control and offset adjustment functional block diagrams a 1 v dd gnd sda scl w1 rdac register 1 serial input register b1 a2 w2 rdac register 2 b2 fuse links 12 / 8 0 4103-001 figure 1. ad5172 functional block diagram v dd gnd sda scl ad0 ad1 w1 rdac register 1 address decode serial input register b1 w2 rdac register 2 b2 fuse links 12 / 8 04103-002 figure 2. ad5173 functional block diagram general description the ad5172/ad5173 are dual-channel, 256-position, one-time programmable (otp) digital potentiometers 1 that employ fuse link technology to achieve memory retention of resistance settings. otp is a cost-effective alternative to eemem for users who do not need to program the digital potentiometer setting in memory more than once. these devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors but with enhanced resolution, solid-state reliabil- ity, and superior low temperature coefficient performance. the ad5172/ad5173 are programmed using a 2-wire, i 2 c?- compatible digital interface. unlimited adjustments are allowed before permanently setting the resistance value. during otp activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer). unlike traditional otp digital potentiometers, the ad5172/ ad5173 have a unique temporary otp overwrite feature that allows for new adjustments even after a fuse is blown. however, the otp setting is restored during subsequent power-up condi- tions. this allows users to treat these digital potentiometers as volatile potentiometers with a programmable preset. 1 the terms digital potentiometer , vr, and rdac are used interchangeably.
ad5172/ad5173 rev. h | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagrams ............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics: 2.5 k ............................................... 3 ? electrical characteristics: 10 k, 50 k, and 100 k ............. 4 ? timing characteristics ................................................................ 6 ? absolute maximum ratings ............................................................ 7 ? esd caution .................................................................................. 7 ? pin configurations and function descriptions ........................... 8 ? typical performance characteristics ............................................. 9 ? test circuits ..................................................................................... 14 ? theory of operation ...................................................................... 15 ? one-time programming (otp) .............................................. 15 ? programming the variable resistor and voltage ................... 15 ? programming the potentiometer divider ............................... 16 ? esd protection ........................................................................... 17 ? terminal voltage operating range ......................................... 17 ? power-up sequence ................................................................... 17 ? power supply considerations ................................................... 17 ? layout considerations ............................................................... 18 ? i 2 c interface .................................................................................... 19 ? write mode ................................................................................. 19 ? read mode .................................................................................. 19 ? i 2 c controller programming .................................................... 20 ? i 2 c-compatible, 2-wire serial bus .......................................... 21 ? level shifting for different voltage operation ...................... 22 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 23 ? revision history 4/09rev. g to rev. h changes to dc characteristicsrheostat mode parameter and to dc characteristicspotentiometer divider mode parameter, table 1 ................................................................................................ 3 12/08rev. f to rev. g changes to otp supply voltage parameter, table 1.................... 3 changes to otp supply voltage parameter, table 2.................... 5 changes to table 5 and table 6 ....................................................... 8 changes to one-time programming (otp) section ................ 15 changes to power supply considerations section, figure 46, and figure 46 caption .................................................................... 17 changes to ordering guide .......................................................... 23 7/08rev. e to rev. f changes to power supplies parameter in table 1 and table 2 ... 3 updated fuse blow condition to 400 ms throughout ............... 5 1/08rev. d to rev. e changes to features .......................................................................... 1 changes to general description .................................................... 1 changes to otp supply voltage and otp supply current in table 1 ................................................................................................ 3 changes to otp supply voltage and otp supply current in table 2 ................................................................................................ 5 added otp program time in table 3 ........................................... 6 changes to table 4 ............................................................................ 7 changes to table 5 and table 6 ....................................................... 8 inserted figure 30 ........................................................................... 13 replaced one-time programming (otp) section ................... 15 replaced power supply considerations section ........................ 17 deleted device programming software section ........................ 20 replaced i 2 c-compatible, 2-wire serial bus section ............... 21 changes to ordering guide .......................................................... 23 6/06rev. c to rev. d changes to features .......................................................................... 1 changes to one-time programming (otp) section................ 15 changes to figure 44 and figure 45............................................. 17 changes to power supply considerations section .................... 18 changes to figure 46 and figure 47............................................. 18 changes to device programming software section .................. 19 updated outline dimensions ....................................................... 24 6/05rev. b to rev. c added footnote 8, footnote 9, and footnote 10 to table 1 ........ 3 added footnote 8 to table 2 ............................................................ 5 changes to table 5 and table 6 ....................................................... 9 changes to power supply considerations section .................... 17 changes to i 2 c-compatible 2-wire serial bus section ............ 23 added level shifting for different voltage operation section ...... 24 updated outline dimensions ....................................................... 25 changes to ordering guide .......................................................... 25 10/04rev. a to rev. b updated format ................................................................. universal changes to specifications ................................................................. 3 changes to one-time programming (otp) section................ 13 changes to power supply considerations section .................... 15 changes to figure 44 and figure 45............................................. 15 changes to figure 46 and figure 47............................................. 16 11/03rev. 0 to rev. a changes to electrical characteristics2.5 k .............................. 3 11/03revision 0: initial version
ad5172/ad5173 rev. h | page 3 of 24 specifications electrical characteristics: 2.5 k v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40c < t a < +125c; unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect ?2 0.1 +2 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect ?14 2 +14 lsb nominal resistor tolerance 3 ?r ab t a = 25c ?20 +55 % resistance temperature coefficient (?r ab /r ab )/?t 35 ppm/c wiper resistance r wb code = 0x00, v dd = 5 v 160 200 dc characteristicspotentiometer divider mode 4 differential nonlinearity 5 dnl ?1.5 0.1 +1.5 lsb integral nonlinearity 5 inl ?2 0.6 +2 lsb voltage divider temperature coefficient (v w /v w )/t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff ?14 ?5.5 0 lsb zero-scale error v wzse code = 0x00 0 4.5 12 lsb resistor terminals voltage range 6 v a , v b , v w gnd v dd v capacitance a, b 7 c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance w 7 c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 8 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs sda and scl input logic high 9 v ih v dd = 5 v 0.7 v dd v dd + 0.5 v input logic low 9 v il v dd = 5 v ?0.5 +0.3 v dd v ad0 and ad1 input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 7 c il 5 pf power supplies power supply range v dd_range 2.7 5.5 v otp supply voltage 9 , 10 v dd_otp t a = 25c 5.6 5.7 5.8 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a otp supply current 9 , 11 , 12 i dd_otp v dd_otp = 5.0 v, t a = 25c 100 ma power dissipation 13 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 33 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics 14 bandwidth, ?3 db bw code = 0x80 4.8 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.1 %
ad5172/ad5173 rev. h | page 4 of 24 parameter symbol conditions min typ 1 max unit v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 1.25 k, r s = 0 3.2 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from the ideal between successive tap positions. parts are guaranteed monoto nic. 3 v a = v dd , v b = 0 v, wiper (v w ) = no connect. 4 specifications apply to all vrs. 5 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operat ing conditions. 6 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. 7 guaranteed by design, but not subject to production test. 8 measured at terminal a. terminal a is open circuited in shutdown mode. 9 the minimum voltage requirement on the v ih is 0.7 v v dd . for example, v ih minimum = 3.5 v when v dd = 5 v. it is typical for the scl and sda resistors to be pulled up to v dd . however, care must be taken to ensure that the minimum v ih is met when the scl and sda are driven directly from a low voltage logic controller without pull-up resistors. 10 different from the operating power supply; the power supply for otp is used one time only. 11 different from the operating current; the supply current for otp lasts a pproximately 400 ms for one time only. 12 see figure 30 for an energy plot during an otp program. 13 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 14 all dynamic characteristics use v dd = 5 v. electrical characteristics: 10 k, 50 k, and 100 k v dd = 5 v 10% or 3 v 10%; v a = v dd ; v b = 0 v; ?40c < t a < +125c; unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect ?1 0.1 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect ?2.5 0.25 +2.5 lsb nominal resistor tolerance 3 r ab t a = 25c ?20 +20 % resistance temperature coefficient (r ab /r ab )/t 35 ppm/c wiper resistance r wb code = 0x00, v dd = 5 v 160 200 dc characteristicspotentiometer divider mode 4 differential nonlinearity 5 dnl ?1 0.1 +1 lsb integral nonlinearity 5 inl ?1 0.3 +1 lsb voltage divider temperature coefficient (v w /v w )/t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff ?2.5 ?1 0 lsb zero-scale error v wzse code = 0x00 0 1 2.5 lsb resistor terminals voltage range 6 v a , v b , v w gnd v dd v capacitance a, b 7 c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance w 7 c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 8 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs sda and scl input logic high 9 v ih v dd = 5 v 0.7 v dd v dd + 0.5 v input logic low 9 v il v dd = 5 v ?0.5 +0.3 v dd v ad0 and ad1 input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 7 c il 5 pf
ad5172/ad5173 rev. h | page 5 of 24 parameter symbol conditions min typ 1 max unit power supplies power supply range v dd_range 2.7 5.5 v otp supply voltage 9 , 10 v dd_otp t a = 25c 5.6 5.7 5.8 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a otp supply current 9 , 11 , 12 i dd_otp v dd_otp = 5.0 v, t a = 25c 100 ma power dissipation 13 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 33 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics 14 bandwidth, ?3 db bw r ab = 10 k, code = 0x80 600 khz r ab = 50 k, code = 0x80 100 khz r ab = 100 k, code = 0x80 40 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k 0.1 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise voltage density e n_wb r wb = 5 k, r s = 0 9 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from the ideal between successive tap positions. parts are guaranteed monoto nic. 3 v a = v dd , v b = 0 v, wiper (v w ) = no connect. 4 specifications apply to all vrs. 5 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operat ing conditions. 6 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. 7 guaranteed by design, but not subject to production test. 8 measured at terminal a. terminal a is open circuited in shutdown mode. 9 the minimum voltage requirement on the v ih is 0.7 v v dd . for example, v ih minimum = 3.5 v when v dd = 5 v. it is typical for the scl and sda resistors to be pulled up to v dd . however, care must be taken to ensure that the minimum v ih is met when the scl and sda are driven directly from a low voltage logic controller without pull-up resistors. 10 different from the operating power supply; the power supply for otp is used one time only. 11 different from the operating current; the supply current for otp lasts a pproximately 400 ms for one time only. 12 see figure 30 for an energy plot during an otp program. 13 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 14 all dynamic characteristics use v dd = 5 v.
ad5172/ad5173 rev. h | page 6 of 24 timing characteristics v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40c < t a < +125c; unless otherwise noted. table 3. parameter symbol conditions min typ max unit i 2 c interface timing characteristics 1 scl clock frequency f scl 400 khz bus-free time between stop and start, t buf t 1 1.3 s hold time (repeated start), t hd;sta t 2 after this period, the first clock pulse is generated. 0.6 s low period of scl clock, t low t 3 1.3 s high period of scl clock, t high t 4 0.6 s setup time for repeated start condition, t su;sta t 5 0.6 s data hold time, t hd;dat 2 t 6 0.9 s data setup time, t su;dat t 7 100 ns fall time of both sda and scl signals, t f t 8 300 ns rise time of both sda and scl signals, t r t 9 300 ns setup time for stop condition, t su;sto t 10 0.6 s otp program time t 11 400 ms 1 see the timing diagrams for the locations of measured va lues (that is, see figure 3 and figure 48 to figure 51). 2 the maximum t hd;dat has to be met only if the device does not stretch the low period (t low ) of the scl signal. timing diagram 04103-0-039 t 1 t 2 t 3 t 8 t 8 t 9 t 9 t 6 t 4 t 7 t 5 t 2 t 10 ps s scl sda p figure 3. i 2 c interface detailed timing diagram
ad5172/ad5173 rev. h | page 7 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to gnd ?0.3 v to +7 v v a , v b , v w to gnd v dd terminal current, ax to bx, ax to wx, bx to wx 1 pulsed 20 ma continuous 5 ma digital inputs and output voltage to gnd 0 v to 7 v operating temperature range ?40c to +125c maximum junction temperature (t jmax ) 150c storage temperature range ?65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec thermal resistance 2 ja for 10-lead msop 200c/w 1 the maximum terminal current is bo und by the maximum current handling of the switches, the maximum power di ssipation of the package, and the maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 the package power dissipation is (t jmax ? t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5172/ad5173 rev. h | page 8 of 24 pin configurations and function descriptions b1 1 a1 2 w2 3 g nd 4 v dd 5 w1 10 b2 9 a2 8 sda 7 scl 6 ad5172 top view (not to scale) 0 4103-0 45 figure 4. ad5172 pin configuration table 5. ad5172 pin function descriptions pin no. mnemonic description 1 b1 b1 terminal. gnd v b1 v dd . 2 a1 a1 terminal. gnd v a1 v dd . 3 w2 w2 terminal. gnd v w2 v dd . 4 gnd digital ground. 5 v dd positive power supply. specified for operation from 2.7 v to 5.5 v. for otp programming, v dd needs to be a minimum of 5.6 v but no more than 5.8 v and to be capable of driving 100 ma. 6 scl serial clock input. positive-edge triggered. requires a pull-up resistor. if this pin is driven directly from a logic controller without a pull-up resistor, ensure that the v ih minimum is 0.7 v v dd . 7 sda serial data input/output. requires a pull-up resistor. if this pin is driven directly from a logic controller without a pull-up resistor, ensure that the v ih minimum is 0.7 v v dd . 8 a2 a2 terminal. gnd v a2 v dd . 9 b2 b2 terminal. gnd v b2 v dd . 10 w1 w1 terminal. gnd v w1 v dd . b1 1 ad0 2 w2 3 gnd 4 v dd 5 w1 10 b2 9 ad1 8 sda 7 scl 6 ad5173 top view (not to scale) 04103-046 figure 5. ad5173 pin configuration table 6. ad5173 pin function descriptions pin no. mnemonic description 1 b1 b1 terminal. gnd v b1 v dd . 2 ad0 programmable address bit 0 for multiple package decoding. 3 w2 w2 terminal. gnd v w2 v dd . 4 gnd digital ground. 5 v dd positive power supply. specified for operation from 2.7 v to 5.5 v. for otp programming, v dd needs to be a minimum of 5.6 v but no more than 5.8 v and to be capable of driving 100 ma. 6 scl serial clock input. positive-edge triggered. requires a pull-up resistor. if this pin is driven directly from a logic controller without a pull-up resistor, ensure that the v ih minimum is 0.7 v v dd . 7 sda serial data input/output. requires a pull-up resistor. if this pin is driven directly from a logic controller without a pull-up resistor, ensure that the v ih minimum is 0.7 v v dd . 8 ad1 programmable address bit 1 for multiple package decoding. 9 b2 b2 terminal. gnd v b2 v dd . 10 w1 w1 terminal. gnd v w1 v dd .
ad5172/ad5173 rev. h | page 9 of 24 typical performance characteristics ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheost a t mode inl (lsb) 1.0 1.5 2.0 128 96 32 64 0 160 192 224 256 code (decimal) v dd = 5.5v t a = 25c r ab = 10k ? v dd = 2.7v 04103-003 figure 6. r-inl vs. code vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rheostat mode dnl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v 04103-004 figure 7. r-dnl vs. code vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode inl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) r ab = 10k ? v dd = 2.7v t a = ?40c, +25c, +85c, +125c v dd = 5.5v t a = ?40c, +25c, +85c, +125c 04103-005 figure 8. inl vs. code vs. temperature ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode dnl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) v dd = 2.7v; t a = ?40c, +25c, +85c, +125c r ab = 10k ? 04103-006 figure 9. dnl vs. code vs. temperature ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 potentiometer mode inl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v 04103-007 figure 10. inl vs. code vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode dnl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v 04103-008 figure 11. dnl vs. code vs. supply voltages
ad5172/ad5173 rev. h | page 10 of 24 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheost a t mode inl (lsb) 1.0 1.5 2.0 128 96 32 64 0 160 192 224 256 code (decimal) r ab = 10k ? v dd = 2.7v t a = ?40c, +25c, +85c, +125c v dd = 5.5v t a = ?40c, +25c, +85c, +125c 04103-009 figure 12. r-inl vs. code vs. temperature ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rheost a t mode dnl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) v dd = 2.7v, 5.5v; t a = ?40c, +25c, +85c, +125c r ab = 10k ? 04103-010 figure 13. r-dnl vs. code vs. temperature ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 fse, full-scale error (lsb) 1.0 1.5 2.0 temperature (c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 v dd = 5.5v, v a = 5.0v r ab = 10k ? v dd = 2.7v, v a = 2.7v 04103-011 figure 14. full-scale error vs. temperature 0 0.75 1.50 2.25 3.00 3.75 4.50 zse, zero-scale error (lsb) temperature (c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 v dd = 5.5v, v a = 5.0v r ab = 10k ? v dd = 2.7v, v a = 2.7v 04103-012 figure 15. zero-scale error vs. temperature i dd , supply curren t ( a ) 0.1 1 10 ?40 ?7 26 59 92 125 temperature (c) v dd = 5v v dd = 3v 04103-013 figure 16. supply current vs. temperature ?20 0 20 40 60 80 100 120 rheostat mode tempco (ppm/c) 128 96 32 64 0 160 192 224 256 code (decimal) r ab = 10k ? v dd = 2.7v t a = ?40c to +85c, ?40c to +125c v dd = 5.5v t a = ?40c to +85c, ?40c to +125c 04103-014 figure 17. rheostat mode tempco r wb /t vs. code
ad5172/ad5173 rev. h | page 11 of 24 ?30 ?20 ?10 0 10 20 potentiometer mode tempco (ppm/c) 30 40 50 128 96 32 64 0 160 192 224 256 code (decimal) r ab = 10k ? v dd = 2.7v t a = ?40c to +85c, ?40c to +125c v dd = 5.5v t a = ?40c to +85c, ?40c to +125c 04103-047 figure 18. ad5172 potentiometer mode tempco v wb /t vs. code ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 10k 1m 100k 10m 0x80 0x40 0x20 0x10 0x08 0x04 0x010x02 04103-048 figure 19. gain vs. frequency vs. code, r ab = 2.5 k ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 1k 100k 10k 1m 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 04103-049 figure 20. gain vs. frequency vs. code, r ab = 10 k ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 1k 100k 10k 1m 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 04103-050 figure 21. gain vs. frequency vs. code, r ab = 50 k ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 1k 100k 10k 1m 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 04103-051 figure 22. gain vs. frequency vs. code, r ab = 100 k ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 10k 1k 100k 1m 10m 100k ? 60khz 50k ? 120khz 10k ? 570khz 2.5k ? 2.2mhz 04103-052 figure 23. ?3 db bandwidth at code = 0x80
ad5172/ad5173 rev. h | page 12 of 24 i dd , supply current (ma) 0.01 1 0.1 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 digital input voltage (v) t a = 25c v dd = 2.7v v dd = 5.5v 04103-057 figure 24. supply current vs. digital input voltage scl v w 04103-053 figure 25. digital feedthrough v w1 v w2 04103-054 figure 26. digital crosstalk v w1 v w2 04103-056 figure 27. analog crosstalk v w 04103-058 figure 28. midscale glitch, code 0x80 to code 0x7f scl v w 04103-055 figure 29. large-signal settling time
ad5172/ad5173 rev. h | page 13 of 24 04103-062 ch1 20.0ma m 200ns a ch1 32.4ma 1 t 588.000ns t channel 1 maximum: 103ma channel 1 minimum: ?1.98ma figure 30. otp program energy for single fuse
ad5172/ad5173 rev. h | page 14 of 24 test circuits figure 31 to figure 38 illustrate the test circuits that define the test conditions used in the product specification tables (see tabl e 1 and table 2 ). v ms a w b dut v+ v+ = v dd 1lsb = v+ /2 n 04103-015 figure 31. potentiometer divider nonlinearity error (inl, dnl) nc i w v ms a w b dut 0 4103-016 nc = no connect figure 32. resistor position nonlinearity error (rheostat operation: r-inl, r-dnl) v ms1 i w = v dd /r nominal v ms2 v w r w = [v ms1 ? v ms2 ]/i w a w b dut 04103-017 figure 33. wiper resistance v ms % pss (%/%) = psrr (db) = 20 log dut () v dd v a v ms a w b v+ v dd % v ms v dd v+ = v dd 10% 04103-018 figure 34. power supply sensitivity (pss, pssr) +5v ?5v w a 2.5v b v out offset gnd dut ad8610 v in 04103-019 figure 35. test circuit for gain vs. frequency w b dut i sw code = 0x00 r sw = 0.1 v i sw 0.1v gnd to v dd 04103-020 figure 36. incremental on resistance v dd a w b dut gnd i cm v cm nc nc 0 4103-021 nc = no connect figure 37. common-mode leakage current v in nc w1 b1 b2 w2 rdac1 a1 rdac2 v dd v ss v out cta = 20 log[v out /v in ] nc = no connect a2 04103-022 figure 38. analog crosstalk
ad5172/ad5173 rev. h | page 15 of 24 theory of operation sda scl a w b fuses en dac reg i 2 c interface comparator one-time program/test control block mux decoder fuse reg 04103-026 figure 39. detailed fu nctional block diagram the ad5172/ad5173 are 256-position, digitally controlled variable resistors (vrs) that employ fuse link technology to achieve memory retention of the resistance setting. an internal power-on preset places the wiper at midscale during power-on. if the otp function is activated, the device powers up at the user-defined permanent setting. one-time programming (otp) prior to otp activation, the ad5172/ad5173 presets to midscale during initial power-on. after the wiper is set to the desired position, the resistance can be permanently set by programming the t bit high, with the proper coding (see table 8 and table 9 ), and one-time v dd_otp . the fuse link technology of the ad517x family of digital potentiometers requires v dd_otp to be between 5.6 v and 5.8 v to blow the fuses to achieve a given nonvolatile setting. however, during operation, v dd can be 2.7 v to 5.5 v. as a result, an external supply is required for one-time programming. the user is allowed only one attempt to blow the fuses. if the user fails to blow the fuses during this attempt, the structure of the fuses can change such that they may never be blown, regardless of the energy applied during subsequent events. for details, see the power supply considerations section. the device control circuit has two validation bits, e1 and e0, that can be read back to check the programming status (see table 7 ). users should always read back the validation bits to ensure that the fuses are properly blown. after the fuses are blown, all fuse latches are enabled upon subsequent power-on; therefore, the output corresponds to the stored setting. figure 39 shows a detailed functional block diagram. table 7. validation status e1 e0 status 0 0 ready for programming. 1 0 fatal error. some fuses are not blown. do not retry. discard this unit. 1 1 successful. no further programming is possible. programming the variable resistor and voltage rheostat operation the nominal resistance of the rdac between terminal a and terminal b is available in 2.5 k, 10 k, 50 k, and 100 k. the nominal resistance (r ab ) of the vr has 256 contact points accessed by the wiper terminal and the b terminal contact. the 8-bit data in the rdac latch is decoded to select one of the 256 possible settings. a w b a w b a w b 04103-027 figure 40. rheostat mode configuration assuming a 10 k part is used, the first connection of the wiper starts at the b terminal for data 0x00. because there is a 50 wiper contact resistance, such a connection yields a minimum of 100 (2 50 ) resistance between terminal w and ter- minal b. the second connection is the first tap point, which corresponds to 139 (r wb = r ab /256 + 2 r w = 39 + 2 50 ) for data 0x01. the third connection is the next tap point, representing 178 (2 39 + 2 50 ) for data 0x02, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 (r ab + 2 r w ).
ad5172/ad5173 rev. h | page 16 of 24 d5 d4 d3 d7 d6 d2 d1 d0 rdac latch and decoder r s r s r s r s a w b 0 4103-028 figure 41. ad5172/ad5173 equivalent rdac circuit the general equation that determines the digitally programmed output resistance between w and b is w ab wb rr d dr += 2 128 )( (1) where: d is the decimal equivalent of the binary code loaded in the 8-bit rdac register. r ab is the end-to-end resistance. r w is the wiper resistance contributed by the on resistance of the internal switch. in summary, if r ab is 10 k and the a terminal is open circuited, the output resistance, r wb , is set according to the rdac latch codes, as listed in table 8 . table 8. codes and corresponding r wb resistance d dec r wb utput state 255 9961 full scale (r ab C 1 lsb + r w ) 128 5060 midscale 1 139 1 lsb 0 100 zero scale (wiper contact resistance) note that in the zero-scale condition, a finite wiper resistance of 100 is present. care should be taken to limit the current flow between w and b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruc- tion of the internal switch contact may occur. similar to the mechanical potentiometer, the resistance of the rdac between wiper w and terminal a also produces a digi- tally controlled complementary resistance, r wa . when these terminals are used, the b terminal can be opened. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is w ab wa rr d dr += 2 128 C256 )( (2) when r ab is 10 k and the b terminal is open circuited, the output resistance, r wa , is set according to the rdac latch codes, as listed in table 9 . table 9. codes and corresponding r wa resistance d dec r wa utput state 255 139 full scale 128 5060 midscale 1 9961 1 lsb 0 10,060 zero scale typical device-to-device matching is process-lot dependent and can vary up to 30%. because the resistance element is processed using thin-film technology, the change in r ab with temperature has a very low temperature coefficient of 35 ppm/c. programming the potentiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper to b and at wiper to a, proportional to the input voltage at a to b. unlike the polarity of v dd to gnd, which must be positive, voltage across a to b, w to a, and w to b can be at either polarity. a v i w b v o 04103-029 figure 42. potentiometer mode configuration if ignoring the effect of the wiper resistance for approximation, connecting the a terminal to 5 v and the b terminal to ground produces an output voltage at the wiper to b, starting at 0 v up to 1 lsb less than 5 v. each lsb of voltage is equal to the vol- tage applied across terminal a and terminal b divided by the 256 positions of the potentiometer divider. the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminal a and terminal b is b a w v d v d dv 256 256 256 )( ? += (3) a more accurate calculation, which includes the effect of wiper resistance, v w , is b ab wa a ab wb w v r dr v r dr dv )( )( )( + = (4) operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. unlike in the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, r wa and r wb , not on the absolute values. therefore, the temperature drift reduces to 15 ppm/c.
ad5172/ad5173 rev. h | page 17 of 24 esd protection all digital inputs, sda, scl, ad0, and ad1, are protected with a series input resistor and parallel zener esd structures, as shown in figure 43 and figure 44 . logic 340 ? gnd 04103-030 figure 43. esd protection of digital pins a, b, w gnd 04103-031 figure 44. esd protection of resistor terminals terminal voltage operating range the ad5172/ad5173 v dd to gnd power supply defines the boundary conditions for proper 3-terminal digital potenti- ometer operation. supply signals present on terminal a, te r m i n a l b, a nd te r m i n a l w t h at e x c e e d v dd or gnd are clamped by the internal forward-biased diodes (see figure 45 ). gnd a w b v dd 04103-032 figure 45. maximum terminal voltages set by v dd and gnd power-up sequence because the esd protection diodes limit the voltage compliance at te r m i n a l a , te r m i n a l b, a nd te r m i n a l w ( s e e figure 45 ), it is important to power v dd /gnd before applying voltage to terminal a, terminal b, and terminal w. otherwise, the diode is forward-biased such that v dd is powered unintentionally and may affect the rest of the users circuit. the ideal power-up sequence is gnd, v dd , digital inputs, and then v a /v b /v w . the relative order of powering v a , v b , v w , and the digital inputs is not important, as long as they are powered after v dd /gnd. power supply considerations to minimize the package pin count, both the one-time pro- gramming and normal operating voltage supplies are applied to the same v dd terminal of the device. the ad5172/ad5173 employ fuse link technology that requires 5.6 v to 5.8 v to blow the internal fuses to achieve a given setting, but normal v dd can be 2.7 v to 5.5 v. such dual-voltage requirements need isolation between the supplies if v dd is lower than the required v dd_otp . the fuse programming supply (either an on-board regulator or rack-mount power supply) must be rated at 5.6 v to 5.8 v and must be able to provide a 100 ma transient current for 400 ms for successful one-time programming. when programming is completed, the v dd_otp supply must be removed to allow normal operation at 2.7 v to 5.5 v; the device consumes only microamps of current. v dd 2.7v 5.7v p1 p1 = p2 = fdv302p, nds0610 r1 10k? p2 c1 10f c2 0.1f a pply for otp only ad5172/ ad5173 0 4103-035 figure 46. isolate 5.7 v otp supply from 2.7 v normal operating supply for example, for those who operate their systems at 2.7 v, use of the bidirectional, low threshold, p-channel mosfets is recom- mended for the isolation of the supply. as shown in figure 46 , this assumes that the 2.7 v system voltage is applied first and that the p1 and p2 gates are pulled to ground, thus turning on p1 and then p2. as a result, v dd of the ad5172/ad5173 approaches 2.7 v. when the ad5172/ad5173 setting is found, the factory tester applies the v dd_otp to both the v dd and the mosfet gates, thus turning p1 and p2 off. to program the ad5172/ad5173 while the 2.7 v source is protected, execute the otp command at this time. when the otp is completed, the tester withdraws the v dd_otp , and the setting of the ad5172 or ad5173 is fixed permanently. the ad5172/ad5173 achieve the otp function by blowing internal fuses. always apply the 5.6 v to 5.8 v one-time pro- gram voltage requirement at the first fuse programming attempt. failure to comply with this requirement may lead to changing the fuse structures, rendering programming inoperable. care should be taken when scl and sda are driven from a low voltage logic controller. users must ensure that the logic high level is between 0.7 v v dd and v dd + 0.5 v. poor pcb layout introduces parasitics that can affect fuse programming. therefore, it is recommended to add a 1 f to 10 f tantalum capacitor in parallel with a 1 nf ceramic capacitor as close as possible to the vdd pin. the type and value chosen for both capacitors are important. these capacitors work together to provide both fast responsiveness and large supply current handling with minimum supply droop during transients. as a result, these capacitors increase the otp programming success by not inhibiting the proper energy needed to blow the internal fuses. additionally, c1 minimizes transient disturbance and low frequency ripple, whereas c2 reduces high frequency noise during normal operation.
ad5172/ad5173 rev. h | page 18 of 24 v dd gnd v dd c1 10f c2 0.1f ad5172 + 04103-036 layout considerations in pcb layout, it is a good practice to employ compact, minimum lead length design. the leads to the inputs should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. figure 47. power supply bypassing
ad5172/ad5173 rev. h | page 19 of 24 i 2 c interface write mode table 10. ad5172 write mode s 0 1 0 1 1 1 1 w a a0 sd t 0 ow x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte table 11. ad5173 write mode s 0 1 0 1 1 ad1 ad0 w a a0 sd t 0 ow x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte read mode table 12. ad5172 read mode s 0 1 0 1 1 1 1 r a d7 d6 d5 d4 d3 d2 d1 d0 a e1 e0 x x x x x x a p slave address byte instruction byte data byte table 13. ad5173 read mode s 0 1 0 1 1 ad1 ad0 r a d7 d6 d5 d4 d3 d2 d1 d0 a e1 e0 x x x x x x a p slave address byte instruction byte data byte table 14. sda bits descriptions bit description s start condition. p stop condition. a acknowledge. ad0, ad1 package pin-programmable address bits. x dont care. w write. r read. a0 rdac subaddress select bit. sd shutdown connects wiper to b terminal and open circuits the a terminal. it does not change the contents of the wiper register. t otp programming bit. logic 1 programs the wiper permanently. ow overwrites the fuse setting and programs the di gital potentiometer to a different setting. upon power-up, the digital potentiometer is preset to either midscale or fuse setting, depending on whether the fuse link was blown. d7, d6, d5, d4, d3, d2, d1, d0 data bits. e1, e0 otp validation bits. 00 = ready to program. 10 = fatal error. some fuses not blow n. do not retry. discard this unit. 11 = programmed successfully. no further adjustments are possible.
ad5172/ad5173 rev. h | page 20 of 24 i 2 c controller programming write bit patterns scl s tart by master sda 01 1 frame 1 slave address byte 01111 frame 2 instruction byte ack by ad5172 r/w a0 sd 0 ow x x x 19 d7 d6 d5 d4 d3 ack by ad5172 frame 3 data byte 19 t stop by master 9 d2 d1 d0 ack by ad5172 04103-040 figure 48. writing to the rdac registerad5172 scl s tart by master sda 01 1 frame 1 slave address byte 0 1 1 ad1 ad0 frame 2 instruction byte ack by ad5173 r/w a0 sd 0 ow x x x 19 d7 d6 d5 d4 d3 ack by ad5173 frame 3 data byte 19 t stop by master 9 d2 d1 d0 ack by ad5173 04103-041 figure 49. writing to the rdac registerad5173 read bit patterns scl s tart by master sda 01 1 frame 1 slave address byte 01111 frame 2 instruction byte ack by ad5172 r/w d7d6 d4d3 d2d1d0 19 e1 e0 x x x ack by master frame 3 data byte 19 d5 stop by master 9 xxx no ack by master 04103-042 figure 50. reading data from a previously selected rdac register in write modead5172 scl s tart by master sda 01 1 frame 1 slave address byte 0 1 1 ad1 ad0 frame 2 instruction byte ack by ad5173 r/w d7d6 d4d3d2d1d0 19 e1 e0 x x x ack by master frame 3 data byte 19 d5 stop by master 9 xxx no ack by master 04103-043 figure 51. reading data from a previously selected rdac register in write modead5173
ad5172/ad5173 rev. h | page 21 of 24 i 2 c-compatible, 2-wire serial bus this section describes how the 2-wire, i 2 c-compatible serial bus protocol operates. the master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high (see figure 48 and figure 49 ). the following byte is the slave address byte, which consists of the slave address followed by an r/ w bit (this bit determines whether data is read from or written to the slave device). the ad5172 has a fixed slave address byte, whereas the ad5173 has two configurable address bits, ad0 and ad1 (see and ). figure 48 figure 49 the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is called the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master reads from the slave device. if the r/ w bit is low, the master writes to the slave device. in write mode, the second byte is the instruction byte. the first bit (msb) of the instruction byte is the rdac subaddress select bit. logic low selects channel 1; logic high selects channel 2. the second msb, sd, is a shutdown bit. a logic high causes an open circuit at terminal a while shorting the wiper to terminal b. this operation yields almost 0 in rheostat mode or 0 v in potentiometer mode. it is important to note that the shutdown operation does not disturb the contents of the register. when brought out of shutdown, the previous setting is applied to the rdac. in addition, during shutdown, new settings can be programmed. when the part is returned from shutdown, the corresponding vr setting is applied to the rdac. the third msb, t, is the otp programming bit. a logic high blows the polyfuses and programs the resistor setting permanently. the otp program time is 400 ms. the fourth msb must always be at logic 0. the fifth msb, ow, is an overwrite bit. when raised to a logic high, ow allows the rdac setting to be changed even after the internal fuses are blown. however, when ow is returned to logic 0, the position of the rdac returns to the setting prior to the overwrite. because ow is not static, if the device is powered off and on, the rdac presets to midscale or to the setting at which the fuses were blown, depending on whether the fuses had been permanently set. the remainder of the bits in the instruction byte are dont cares (see figure 48 and figure 49 ). after acknowledging the instruction byte, the last byte in write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 3 ). in read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference from the write mode, where there are eight data bits followed by an acknowledge bit). similarly, transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 50 and figure 51 ). note that the channel of interest is the one that is previously selected in write mode. if users need to read the rdac values of both channels, they must program the first channel in write mode and then change to read mode to read the first channel value. after that, the user must return to write mode with the second channel selected and read the second channel value in read mode. it is not necessary for users to issue the frame 3 data byte in write mode for subsequent readback operations. refer to figure 50 and figure 51 for the programming format. following the data byte, the validation byte contains two valida- tion bits, e0 and e1 (see table 7 ). these bits signify the status of the one-time programming (see figure 50 and figure 51 ). after all data bits are read or written, the master establishes a stop condition. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition (see figure 48 and figure 49 ). in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master brings the sda line low before the 10 th clock pulse and then brings the sda line high to establish a stop condition (see figure 50 and figure 51 ). a repeated write function provides the user with the flexibility of updating the rdac output multiple times after addressing and instructing the part only once. for example, after the rdac has acknowledged its slave address and instruction bytes in write mode, the rdac output is updated on each successive byte. if different instructions are needed, however, the write/read mode must restart with a new slave address, instruction, and data byte. similarly, a repeated read function of the rdac is also allowed.
ad5172/ad5173 rev. h | page 22 of 24 multiple devices on one bus (ad5173 only) level shifting for different voltage operation figure 52 shows four ad5173 devices on the same serial bus. each has a different slave address because the states of the ad0 and ad1 pins are different. this allows each device on the bus to be written to or read from independently. the master device output bus line drivers are open-drain pull-downs in a fully i 2 c-compatible interface. if the scl and sda signals come from a low voltage logic controller and are below the minimum v ih level (0.7 v v dd ), level shift the signals for read/write communications between the ad5172/ad5173 and the controller. figure 53 shows one of the implementations. for example, when sda1 is at 2.5 v, m1 turns off, and sda2 becomes 5 v. when sda1 is at 0 v, m1 turns on, and sda2 approaches 0 v. as a result, proper level shifting is established. it is best practice for m1 and m2 to be low threshold n-channel power mosfets, such as the fdv301n from fairchild semiconductor. sda sda ad1 ad0 master scl scl ad5173 sda ad1 ad0 scl ad5173 sda ad1 ad0 scl ad5173 sda 5v r p r p 5v 5v 5v ad1 ad0 scl ad5173 04103-044 2.5v controller 2.7v to 5.5v ad5172/ ad5173 r p r p r p r p v dd1 = 2.5v v dd2 = 5v g g s d m1 s d m2 sda1 scl1 sda2 scl2 04103-061 figure 52. multiple ad5173 devices on one i 2 c bus figure 53. level shifting for different voltage operation
ad5172/ad5173 rev. h | page 23 of 24 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 54. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model 1 r ab (k) temperature range package description package option branding ad5172brm2.5 2.5 ?40c to +125c 10-lead msop rm-10 dcy ad5172brm2.5-rl7 2.5 ?40c to +125c 10-lead msop rm-10 dcy ad5172brmz2.5 2 2.5 ?40c to +125c 10-lead msop rm-10 dcr ad5172brm10 10 ?40c to +125c 10-lead msop rm-10 dcz ad5172brm10-rl7 10 ?40c to +125c 10-lead msop rm-10 dcz ad5172brmz10 2 10 ?40c to +125c 10-lead msop rm-10 dct ad5172brmz10-rl7 2 10 ?40c to +125c 10-lead msop rm-10 dct ad5172brm50 50 ?40c to +125c 10-lead msop rm-10 dcx ad5172brmz50 2 50 ?40c to +125c 10-lead msop rm-10 dcu ad5172brmz50-rl7 2 50 ?40c to +125c 10-lead msop rm-10 dcu ad5172brm100 100 ?40c to +125c 10-lead msop rm-10 dcw ad5172brmz100 2 100 ?40c to +125c 10-lead msop rm-10 dcv AD5172BRMZ100-RL7 2 100 ?40c to +125c 10-lead msop rm-10 dcv ad5173brm2.5 2.5 ?40c to +125c 10-lead msop rm-10 dcm ad5173brm2.5-rl7 2.5 ?40c to +125c 10-lead msop rm-10 dcm ad5173brmz2.5 2 2.5 ?40c to +125c 10-lead msop rm-10 dch ad5173brmz2.5-rl7 2 2.5 ?40c to +125c 10-lead msop rm-10 dch ad5173brm10 10 ?40c to +125c 10-lead msop rm-10 dcq ad5173brm10-rl7 10 ?40c to +125c 10-lead msop rm-10 dcq ad5173brmz10 2 10 ?40c to +125c 10-lead msop rm-10 dcl ad5173brmz10-rl7 2 10 ?40c to +125c 10-lead msop rm-10 dcl ad5173brm50 50 ?40c to +125c 10-lead msop rm-10 dcn ad5173brm50-rl7 50 ?40c to +125c 10-lead msop rm-10 dcn ad5173brmz50 2 50 ?40c to +125c 10-lead msop rm-10 dcj ad5173brmz50-rl7 2 50 ?40c to +125c 10-lead msop rm-10 dcj ad5173brm100 100 ?40c to +125c 10-lead msop rm-10 dcp ad5173brm100-rl7 100 ?40c to +125c 10-lead msop rm-10 dcp ad5173brmz100 2 100 ?40c to +125c 10-lead msop rm-10 dck 1 the part has a yww or #yww label and an assembly lot number label on the bottom side of the package. the y shows the year that the part was made; for example, y = 5 means the part was made in 2005. ww sh ows the work week that the part was made. 2 z = rohs compliant part.
ad5172/ad5173 rev. h | page 24 of 24 notes purchase of licensed i 2 c components of analog devices, inc., or one of its sublicensed associated companies conveys a license for the purchaser under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2003C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04103-0-4/09(h)

▲Up To Search▲

Price & Availability of AD5172BRMZ100-RL7

	To Download AD5172BRMZ100-RL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .